1. Field of the Invention
Methods and apparatuses consistent with the present invention relate to performing speculative load instructions of a processor. More particularly, apparatuses and methods consistent with the present invention relate to performing speculative load instructions of a processor and improving performance of the processor by a simple software-like improvement while the processor performs speculative load instructions without addition of a hardware.
2. Description of Related Art
A processor refers to a Central Processing Unit (CPU) and is a core device of a computer system which controls command words, interpretation, and processing of calculations, comparison, and the like, of data. The processor comprises a processor core which performs operation instructions, and a memory in which instructions and data to be processed by the processor core are stored.
The processor core fetches branch instructions from the memory and decodes the branch instructions when performing them.
In performing load instructions by a conservative method of a related art processor, no operation instruction is performed during an occurrence of a delay while the branch instruction is being performed. Thus, performance deterioration of the processor is caused for a period of time during an occurrence of a delay while the branch instruction is being performed.
Furthermore, in performing a speculative load instruction which has been suggested to solve problems occurred by the conservative method, when the load instruction is performed by a mis-speculative method, the processor core disadvantageously accesses a memory-mapped input/output (I/O) register which is mapped in a memory, thereby destroying data of an I/O device or inducing a generation of a page fault.
Also, in another related art method of performing a speculative load instruction, only load instructions to which an identifier is added are limitedly performed by a speculation method. In such a method, occurrence of an exception such as corruption of I/O data, or a page fault is determined by using a check instruction before using data values stored in a register. When no exception occurs, the data values stored in the register are normally used. However, when an exception occurs, the occurrence of the exception is handled through a method specified by the check instruction before using register values since fault data values would be stored in the register.
However, in the methods described above, there is a disadvantage in that since existence of an occurrence of an exception is stored and then a recovery instruction needs to be performed by using the check operation instruction at the time of occurrence of an exception, complex configuration is required in terms of hardware and a compiler, thereby generating additional cost.
Therefore, in accordance with the present invention, occurrence of an exception may be handled by only a simple software-like method when a load instruction is operated by a speculative method.